AMX AXP-AI8 ANALOG 8-INPUT BOARD Manuale Utente Scaricare il pdf (Pagina 13)

DNA/DNR-AI-217 Simultaneous Sampling Differential Analog Input Board

Chapter 1 9

Introduction

Tel: 508-921-4600 www.ueidaq.com Vers: 4.5

Date: April 2013 DNx-AI-217 Chap1x.fm

United Electronic Industries, Inc.

inputs are first sampled by the ADC simultaneously and gain/offset adjustments

are applied. The CJC channel is sampled once each decimation cycle. More

information on A/D conversion is provided in the next section.

The dedicated CJC channel that can be used for reading from a built-in CJC

sensor on the DNA-STP-AI-U or AI-207TC accessory terminal panel. Static CJC

compensation may be used when no CJC sensor is available, such as when it is

connected to a DNA-STP-37 accessory panel. When used with DNA-STP-AI-U

Universal Terminal Panel, the DNx-AI-217 layer also offers a direct connection

for thermocouples and open TC detection. The STP-AI-U accessory panel also

provides excitation for 2-wire and 4-wire RTD measurements. For details, see

the User Manual for the STP-AI-U screw terminal panel. The AI-217’s versatile

design allows it to achieve an exceptional cost/performance ratio, making it an

ideal solution for precise temperature measurement over a long period of time.

Figure 1-2. Logical Modules of the DNx-AI-217 Controller

The samples from A/D converters travel across an opto-isolated barrier into the

AI-217’s controller chip. The structure of on-chip logical modules is illustrated in

the block diagram shown in Figure 1-2.

Samples from the A/D are passed to a FIR Module that provides both a finite-

input-response filter and data decimation, and then into the FIR Synchronization

module, which streams data/samples into the input Channel List buffer; this is

the data that is retrieved to your computer application when using function calls

like the ones listed in Chapter 3. It does not guarantee that channels will be

FIR Sync Module

PGA Error Interrupts

adc-rdy

adc-sdo

adc-sync

adc-sclk

adc-mclk

pga-d

pga-clk

Output Channel List

Only conversion clock used.

Each channel has its own

data storage, but all 4

channels share the same

coefficients and decimation

ratio. Software-configured.

Receives data from

four 4-chan FIR units

plus CJC. Streams

data into Input CL.

Output sample and

their channel number.

4-channel FIR Module

[128-taps max for 217-1;

512-taps max for 217-803]

24-bit FIR

Coeff.

24-bit

Data

Input Channel List

for AI-217

PGA280 Access Module

Configure two master and

fourteen slave PGA280s.

Output conversion clock

Used as 8x master clock

source for ADCs.

to AD7766 ADC and CJC

ADC Reader Module

Simultaneous read from

all 16+1 channels.

Per-channel offset &

gain adjustments.

Clock Divider

Divides input clock source to

use as 8x ADC clock source.

Source is software-selectable.

to PGA280s

Input Clock Source

21.12M, 25.6M, 66MHz, or custom freq.

Standard DNA Logic

found on every layer.

Provides DMA access

to ADC Reader, FIR

Module, PGA Module,

and other components.

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