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¡ Semiconductor MSM82C59A-2RS/GS/JS
FEDL82C59A-2-03
SYSTEM INTERFACE
BASIC OPERATION DESCRIPTION
Data transfers between the 82C59A-2 internal registers and the data bus are listed below.
A
0
Address Bus
Control Bus
D
7
- D
0
8 bits
WR INTA
Data Bus
MSM82C59A-2
CS RD INT
Cascade
Address Bus
CAS
0
CAS
1
CAS
2
SP/EN IR
0
IR
1
IR
2
IR
3
IR
4
IR
5
IR
6
IR
7
Slave
Program/Enable
Buffer
Interrupt Requests
1
0
0
0
0
A
0
Function
1
¥
¥
¥
¥
0
0
1
¥
D
4
¥
¥
¥
¥
¥
0
1
¥
¥
D
3
¥
¥
¥
¥
0
1
1
1
0
RD
1
1
¥
0
1
0
0
0
1
WR
0
1
¥
0
IRR, ISR, or Poll Word Æ Data Bus
IMR Æ Data bus
Data Bus Æ OCW2
Data Bus Æ OCW3
Data Bus Æ 1CW1
Data Bus Æ OCW1, ICW2, ICW3, ICW4
Data Bus Set to High Impedance (when INTA = 1)
Combinations Prohibited
CS
0
0
0
0
0
0
0
1
¥
Opearation
Read
Read
Write
Write
Write
Write
—
—
- COE305 1
- Lab Manual 1
- Microcomputer Systems Design 2
- Table of Contents 3
- 8086 Microprocessor System 4
- Interfacing the Clock 5
- Generator to the CPU 5
- 1.4 Procedure 6
- MXMN / (pin 33) 7
- Designing the Bus System 8
- 2.4 Procedure 9
- COE305 LAB MANUAL 10
- Designing the Memory 11
- 3.4 Procedure 12
- EMR ), memory write 13
- Interfacing I/O Ports 15
- 4.4 Procedure 16
- Testing the 80806 18
- Microcomputer System 18
- 5.2 Equipment 19
- 5.3 Procedure 19
- 5.4 Debugging the System 21
- Exercises 22
- Flight 8086 Training Board 24
- 1.1 Background 25
- 26
- 1.4 The First Program 27
- -M W 0050:0100 29
- 0050:0100 0002 0005 29
- 0050:0102 0003 0007 29
- 0050:0104 0005 29
- Conducting Simple I/O 33
- Operations Using Flight 86 33
- Training Kit 33
- 2.1 Background 34
- 2.2 The Application Board 34
- Table 2.1: Mode Switches 35
- Application Board 37
- Generating Timing 40
- Sequences 40
- 3.1 Background 41
- 3.2 Software Delays 41
- and segment) of 47
- Experiment 50
- 4.1 Background 51
- 4.2 A/D Conversion 51
- 4.3 D/A Conversion 53
- Controlling DC Motors 57
- 5.1 DC Motor 58
- Interfacing a Hyper 62
- Terminal to the Flight 86 62
- 6.1 Background 63
- Table 6.1: 8251 Status Word 65
- Mini Project 69
- Appendices 70
- 16-BIT HMOS MICROPROCESSOR 71
- 8086/8086-2/8086-1 71
- ). Only the pin 75
- FUNCTIONAL DESCRIPTION 76
- General Operation 76
- MINIMUM AND MAXIMUM MODES 77
- 231455–5 78
- 231455–6 78
- 231455–8 79
- External Interface 80
- 231455–9 81
- Basic System Timing 82
- ABSOLUTE MAXIMUM RATINGS* 84
- D.C. CHARACTERISTICS (8086: T 84
- A.C. CHARACTERISTICS (8086: T 85
- TIMING RESPONSES 86
- WAVEFORMS 87
- WAVEFORMS (Continued) 88
- A.C. CHARACTERISTICS 89
- MAXIMUM MODE 92
- 231455–15 92
- 231455–21 95
- Mnemonics 96
- Intel, 1978 96
- offset-high 99
- DATA SHEET REVISION REVIEW 100
- CMOS Clock Generator Driver 101
- Functional Diagram 102
- Pin Description 103
- Functional Description 104
- Die Characteristics 105
- DC Electrical Specifications V 105
- Capacitance T 105
- Operating Conditions 105
- AC Electrical Specifications V 106
- Timing Waveforms 107
- Test Load Circuits 108
- Burn-In Circuits 109
- Sales Office Headquarters 110
- Metallization Mask Layout 110
- DM74LS373/DM74LS374 111
- Edge-Triggered Flip-Flops 111
- Function Tables 112
- DM54/74LS373 112
- DM54/74LS374 112
- Logic Diagrams 113
- 5 www.fairchildsemi.com 115
- 7 www.fairchildsemi.com 117
- DM74LS245 118
- 3-STATE Octal Bus Transceiver 118
- Electrical Characteristics 119
- Switching Characteristics 120
- ¡ Semiconductor 121
- CIRCUIT CONFIGURATION 122
- PIN CONFIGURATION (TOP VIEW) 123
- ABSOLUTE MAXIMUM RATINGS 124
- OPERATING RANGE 124
- RECOMMENDED OPERATING RANGE 124
- DC CHARACTERISTICS 124
- AC CHARACTERISTICS 125
- TIMING DIAGRAM 126
- PIN DESCRIPTION 129
- Mode definition of group A 131
- FUNCTIONAL BLOCK DIAGRAM 145
- OPERATING RANGES 147
- TIMING CHART 149
- DESCRIPTION OF PIN FUNCTIONS 150
- SYSTEM INTERFACING 150
- DESCRIPTION OF OPERATION 151
- FEDL82C59A-2-03 161
- BLOCK DIAGRAM 161
- INTA Sequence (85 mode) 166
- INTA Sequence (86 mode) 166
- PIN FUNCTION DESCRIPTION 167
- SYSTEM INTERFACE 168
- BASIC OPERATION DESCRIPTION 168
- OPERATION DESCRIPTION 169
- Before Rotation 179
- After Rotation 179
- FUNCTION 188
- ABSOLUTE MAXIMUM RATING 196
- OPERATING RANGE 196
- DC CHARACTERISTICS 196
- CPU Bus Interface Part 197
- Serial Interface Part 198
- Data Out Active 200
- Data Float Data Float 200
- START BIT 201
- STOP BIT 201
- (Note 2) 202
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